1. Field of the Invention
The present invention relates generally to integrated circuit (IC) devices and, more particularly, to a method for forming a redistribution layer of a flip chip IC device including structures formed by such method.
2. Description of the Related Art
Currently, in order to remain competitive in the IC industry, IC designers must continuously reduce the overall size and corresponding cost of IC devices. Thus, IC device features continue to shrink. As a result of this trend toward smaller feature sizes, circuit density has correspondingly increased. That is, many IC designers pursue ways to significantly increase the feature density so as to take full advantage of significant decreases in feature size. As a result, IC designers must also continue to increase the I/O pin density so as to take full advantage of significant increases in feature density. With these goals in mind, IC chip designers have developed a wide variety of package designs to maximize I/O pin density.
One package design includes an array of pads to provide interconnections between the IC devices within the package and other electrical components or IC devices external to the package. Flip chip type packages are an example of packages that use arrays of interconnecting pads. An array configuration allows the designer to utilize the entire package area for I/O pin placement, as opposed to package designs which merely provide I/O pins around the package periphery.
Although flip chip IC designs have many advantages, a problem with flip chip IC designs is skew between signals that are traveling along adjacent traces on a redistribution layer. Skew is defined as the difference in propagation times of various signals as the signals traverse from one point to another. The redistribution layer is a layer that is formed over a topmost layer of a flip chip IC to enable electrical interconnection to a particular package via solder bumps. The redistribution layer has a number of traces that interconnect a plurality of pads that are routed to each of the solder bumps that are arranged in an array format. It has been found that the skew between adjacent traces is directly related to the differences in capacitance and resistance associated with each of the traces, which are typically of varying lengths.
Another problem with conventional redistribution layers is that of variable coupled noise that occurs between adjacent traces of varying lengths on the redistribution layer. It is believed that the variation in coupled noise is related to the difference in resistance between I/O lines.
FIG. 1A is a top view of a conventional redistribution layer 100 that includes a plurality of patterned metallization features. These patterned features typically include slot pads 102 which are interconnected to bump pads 104 via traces. For example, a trace 106 is used to interconnect slot pad 102a to bump pad 104a, and a trace 108 is used to interconnect slot pad 102b to bump pad 104b. As shown, slot pads 102 are arranged around the periphery of the redistribution layer 100, while bump pads 104 are arranged in an array configuration within the interior region of the redistribution layer 100. As mentioned above, the purpose of the redistribution layer 100 is to distribute signals that are received from the slot pads 102 to each of the bump pads 104. Generally, the slot pads 102 are connected to underlying devices (not shown) that are fabricated in a flip chip IC that underlies the redistribution layer 100. Once the redistribution layer 100 is formed over the flip chip IC, solder balls are connected to each of the bump pads 104 to enable interconnect to the I/O pins of a given package.
FIG. 1B is a cross section view of a semiconductor device having a plurality of conventionally fabricated layers. IC devices, such as transistors are generally formed on a the silicon substrate and then interconnected with subsequently formed metallization layers and conductive vias. As shown, a base oxide 112 (e.g., SiO.sub.2) is deposited over the silicon substrate. Next, a first metallization layer 114 is deposited and patterned over the base oxide 112 to form a first level of interconnect lines. A first dielectric layer 116 is then formed over the first metallization layer 114. The process may then be repeated to form a plurality of metallization and dielectric layers as needed for a particular application. Once the intermediate layers are fabricated, a top most dielectric layer 118 is formed.
The redistribution layer 100 is typically located between the top most dielectric layer 118 and a package (not shown). As mentioned above, the redistribution layer 100 is in the form of a patterned metallization layer that includes bump pads 104, traces (e.g., 106 and 108), and slot pads 102.
Bumps 110 are then formed on each of the bump pads 104 using conventional solder ball application techniques. Each dielectric layer may then contain a via network for interconnecting the IC devices that are formed on the substrate. For example, a via network 117 connects an underlying metallization layer (not shown) with the redistribution layer 100. Other via networks (not shown) are then utilized to connect other underlying metallization layers to IC devices that are formed on the substrate.
The dielectric and metallization layers are typically patterned using well known photolithography techniques. Patterning is typically accomplished by depositing a photoresist layer over the layer to be patterned, and then selectively exposing the photoresist to light through a patterned reticle. Once exposed, the photoresist is developed to form a photoresist mask that is used in etching layers that are exposed and not covered by the photoresist material.
As described above, one disadvantage with the conventional redistribution layer 100 of FIGS. 1A and 1B is that the resulting traces 106 and 108 have varying trace lengths. For example, trace 106 is significantly shorter than trace 108. Variable trace lengths may result in unacceptable signal skew values between adjacent trace signals. For example, the innermost bump pad 104b and the outermost bump pad 104a will have an unacceptable signal skew between them because trace 108 is much longer than trace 106.
In order to minimize the aforementioned skew and noise problems, designers have been forced to limit the number of bumps pads 104 contained in the redistribution layer 100. When the number of bump pads is reduced, the result is to reduce the difference in length between the outermost trace and innermost trace. Although this technique is well suited to somewhat reduce the skew and noise problems to levels that comply with specifications requirements, the allowable I/O density of a redistribution layer 100 will also necessarily decrease.
To further illustrate the aforementioned skew problems, FIG. 1C provides a representation of skew between two conventional flip devices that have redistribution layers 100. After bumps 110 are placed upon the bump pads 104 of the redistribution layers 100, the flip chip device is then inverted onto a PC Board 120. The bumps 110 of a Chip A are then electrically connected to the bumps 110 of a Chip B through electrical traces that are patterned on the PC Board 120. For example, bump 110a of the Chip A may be connected to bump 110a of the Chip B. Likewise, bump 110b of the Chip A may be connected to bump 110b of the Chip B.
Because bump 110a has a longer trace than bump 110b, signal skew is consequently introduced between the chips. As a result, if the skew grows to levels that exceed the specification, performance problems may result when signals are passed between chips. In some cases, a significant amount of skew may cause Chip B to misread the signals received from Chip A and, consequently, cause Chip B to execute invalid operations.
FIG. 1D is a representation of skew and variable voltage levels for different I/O signals within a conventional redistribution layer 100. FIG. 1D illustrates skew 158 between different I/O signals (152, 154, 156). As shown, each I/O signal has a different overshoot that results in skew 158. That is, each I/O signal has a different rise time. This variation in rise time, commonly referred to as an overshoot, contributes to the signal skew 158 between I/O signals.
Additionally, FIG. 1D represents another disadvantage of the conventional redistribution layer 100--the variation of coupled noise between I/O signals. The ability to control the coupled noise is particularly important for certain types of I/O drivers. Since coupled noise on a particular I/O signal depends on that signal's voltage level, which level is affected by the resistance of the signal's trace within the redistribution layer 100, a signal's voltage level will be different for each respective trace length. For example, a trace length of 0.21 mm has a voltage level of about 1.94 V, while a trace length of 2.1 mm has a voltage level of about 1.84. See FIG. 1D. This difference in voltage levels results in a difference in coupled noise.
To correct the problems of skew and noise, the IC designer must sacrifice I/O density. In other words, the IC designer must face trade-offs between increasing density and controlling coupled noise and skew. In balancing these needs, IC designers typically choose between a number of conventional approaches for designing the redistribution layers 100.
One approach for balancing these needs is to use traces that have the same lengths, and thereby relax the density requirements. Although this works fine for devices in which increased density is not an issue, this approach requires a substantial amount of customization of the redistribution layer 100. Of course, such customization is not always suitable in many applications, such as application specific integrated circuit (ASIC) devices, in which budget constraints limit the amount of time and money available to complete a device. In sum, this solution results in a huge decrease in I/O density and an increase in design complexity, time, and cost.
Accordingly, in view of the foregoing, there is a need for a method of fabricating standardized redistribution layers that allow for variable length traces while substantially minimizing signal skew and coupled noise problems, while providing a high I/O density.